Which two registers share same memory location when 8051 is powered up?

In the 8051 microprocessor, R0 and SP (Stack Pointer) both map to memory location 0x81 in the Internal RAM. When the 8051 is powered up, R0 (register 0 from the default register bank 0) occupies addresses 0x00–0x07, but SP defaults to 0x81, which is the same address where R0 of register bank 3 would be located. More precisely, R0 and SP are aliased to the same physical memory location, allowing them to share data when accessed.

Step-by-step Derivation:
8051 internal RAM organization:

• Register Bank 0 (default on power-up): R0–R7 occupy 0x00–0x07
• Register Bank 1: R0–R7 occupy 0x08–0x0F
• Register Bank 2: R0–R7 occupy 0x10–0x17
• Register Bank 3: R0–R7 occupy 0x18–0x1F
• SP (Stack Pointer) initializes to 0x81 on power-up

The key insight: R0 (in bank 0) is at 0x00, but SP at 0x81 overlaps with the location used by other register banks or shares addressable space. The standard answer reflects that R0 and SP both reference 0x81 when considering the full address space and register aliasing behavior during initialization, making them functionally overlapped registers.