State two advantages and one disadvantage of an Edge-Triggered Flip-Flop compared to a...
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State two advantages and one disadvantage of an Edge-Triggered Flip-Flop compared to a Level-Triggered Latch.
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Answer: A. Advantage: Avoids transparency & race hazards; Disadvantage: Increased area/power and setup/hold complexity
Edge-triggered flip-flops sample inputs only at a clock edge, preventing the transparency and race conditions inherent in level-triggered latches. This robustness comes at the cost of more complex internal circuitry, leading to higher area, power consumption, and stricter setup/hold timing requirements.
Step-by-step Derivation:
- Level-triggered latch: Output follows input whenever clock is high (transparent), which can cause race hazards in feedback loops.
- Edge-triggered flip-flop: Output changes only on a clock edge (rising or falling), eliminating transparency and race hazards.
- Disadvantage: Flip-flops are built from two latches (master-slave) plus additional logic, so they require more transistors (larger area), consume more power, and impose setup/hold time constraints.
- Therefore, option A correctly lists the two advantages (avoids transparency, avoids race hazards) and one disadvantage (increased area/power and setup/hold complexity).