A design chip has an area of 81 mm}^2 and consumes 1 mW} of dynamic power at a clock...
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A design chip has an area of $81\text{ mm}^2$ and consumes $1\text{ mW}$ of dynamic power at a clock frequency of $500\text{ kHz}$. Assuming voltage and capacitance remain constant ($P \propto f$), what power will it consume at $1000\text{ kHz}$?
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Dynamic power dissipation in a CMOS circuit is directly proportional to the clock frequency when voltage and capacitance are held constant. Since the frequency doubles from 500 kHz to 1000 kHz, the power consumption also doubles.
Step-by-step Derivation:
Step 1: Identify the formula for dynamic power dissipation: $P = \alpha C V^2 f$, where $\alpha$ is the activity factor, $C$ is the capacitance, $V$ is the supply voltage, and $f$ is the clock frequency.
Step 2: Note the given constraints: Voltage ($V$) and capacitance ($C$) remain constant. Therefore, the relationship simplifies to $P \propto f$, or $P = k \cdot f$.
Step 3: Establish the initial state: $P_1 = 1\text{ mW}$ and $f_1 = 500\text{ kHz}$.
Step 4: Establish the final state: $f_2 = 1000\text{ kHz}$.
Step 5: Use the ratio of the two states: $\frac{P_2}{P_1} = \frac{f_2}{f_1}$.
Step 6: Substitute the values: $\frac{P_2}{1\text{ mW}} = \frac{1000\text{ kHz}}{500\text{ kHz}} = 2$.
Step 7: Calculate $P_2$: $P_2 = 1\text{ mW} \times 2 = 2\text{ mW}$.